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Minos Computing Library

Supporting Extremely Heterogeneous Computing in HPC, AI, and Data Analytics

PPoPP'23 -- February 26th, 2023

Programming extremely heterogeneous system with MCL

Logistics: Sunday February 26th, 2023 -- TBD

Objectives: This tutorial provides an overview of the MCL programming environment and a step- by-step guide to write, build, and test an MCL program in a multi-device environment. At the end of this tutorial, attendees should be able to run their MCL code on their laptops and scale out their code on more complex systems, both larger workstations and power-efficient embedded systems.

Abstract: Emerging applications in different domains, from scientific simulations and machine- learning to data-analytics and signal-processing, pose new challenges and requirements to industry and research communities. Specialization has become a fundamental pillar for the design of future high-end systems: modern supercomputers feature several accelerators (e.g., GPUs); military systems employ domain-specific SoC and ASICs; industries have introduced specialized hardware for machine-/deep-learning. This high level of specialization results in extremely heterogeneous systems that are complicated to design, test, and program. This tutorial introduces the Minos Computing Library (MCL), a new programming environment for efficient programming of extremely heterogeneous systems. MCL provides a task-based abstraction that simplifies programming and hides architectural details while the runtime supports asynchronous execution of tasks from concurrent applications. The MCL scheduler manages computing resources, performs automatic load balancing, and utilizes locality-aware scheduling. MCL increases performance portability by transparently scaling applications developed on personal desktops to large workstations and supercomputers as well as power- efficient embedded systems. This tutorial will demonstrate how MCL can be used to program and drive multiple heterogeneous classes of devices, such as GPGPU, FPGA, and DL accelerators, and manage multiple devices within a system (e.g., multi-GPU systems).

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Time (PST) Topic Presenter Material
1.20-1.50 Introduction
1.50-2.35 Hands-on Session
2.35-3.20 MCL on FPGA and NVDLA Accelerators
3.20-3.40 Coffee Break
3.40-4.25 MCL enabling Co-Design
4.25-5.20 Programming with Rust
5.20-5.40 Q&A and Conclusions All